Testing Static Random Access Memories Defects, Fault Models and Test Patterns

Embedded memories are one of the fastest growing segments oftoday's new technology market. According to the 2001 InternationalTechnology Roadmap for Semiconductors, embedded memories will continueto dominate the increasing system on chip (SoC) content in the nextseveral years, approaching 94% of the SoC area in about 10 years.Furthermore, the shrinking size of manufacturing structures makesmemories more sensitive to defects. Consequently, the memory yieldwill have a dramatic impact on the overall Defect-per-million level, hence on the overall SoC yield. Meeting a high memory yield requiresunderstanding memory designs, modeling their faulty behaviors, designing adequate tests and diagnosis algorithms as well as efficientself-test and repair schemes."Testing Static Random Access Memories" covers testing of one ofthe important semiconductor memories types; it address testing ofstatic random access memories (SRAMs), both single-port andmulti-port. It contributes to the technical acknowledge needed bythose involved in memory testing, engineers and researchers. The bookbegins with outlining the most popular SRAMs architectures. Then, thedescription of realistic fault models, based on defect injection andSPICE simulation, are introduced. Thereafter, high quality and lowcost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with somepreliminary test results showing the importance of the new tests inreducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies isalso discussed.Features: