• On-Chip Training NPU - Algorithm, Architecture and SoC Design

On-Chip Training NPU - Algorithm, Architecture and SoC Design

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Overview

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

Product Details

ISBN-13: 9783031342363
ISBN-10: 3031342364
Publisher: Springer Nature Switzerland
Publication date: 2023-07-28
Edition description: 1
Pages: 237
Product dimensions: Height: 9.21 inches, Length: 6.14 inches, Weight: 1.23238404458 pounds, Width: 0.63 inches
Author: Donghyeon Han, Hoi-Jun Yoo
Language: en
Binding: Hardcover

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