Formal Specification and Verification of Digital Systems

The necessity of producing error-free integrated circuits follows from the cost and inconvenience which ensue if errors are found to be present in a complete circuit. As a result of this need and of the problems associated with simulation methods, formal verification techniques are now emerging as a realistic alternative. Intended to serve as a stand-alone introduction to the field, this book develops in detail two complementary approaches to hardware verification, involving the use of higher order logic and process algebra, respectively. The material is divided into three parts. The first concerns itself with the role of hardware specification, and specification languages, in the formal verification process. The traditional validation technique, that of simulation, is discussed and is contrasted with formal hardware verification. The second part describes the use of higher order logic in the specification and verification of hardware. Finally, the book presents a particular process calculus as an appropriate formalism for rigorous design analysis. In both the second and the third parts the fundamental concepts of logic and process calculi are introduced and techniques for using them are presented by the use of an extensive set of examples.